The present invention relates to a field effect transistor constituted of a compound semiconductor, and particularly to a field effect transistor having a double recess structure.
In a field effect transistor (FET), a double recess structure is widely used for the purpose of improvement in breakdown voltage. The double recess structure means a structure in which recesses of two steps are formed around a gate electrode. The recess provided outside is called an outer recess section, and the recess provided inside is called an inner recess section.
A general compound semiconductor FET having a double recess structure has a structure wherein an undoped AlGaAs buffer layer, an InGaAs channel layer, an undoped AlGaAs spacer layer, an Si doped AlGaAs carrier supply layer, an undoped AlGaAs Schottky contact layer, and an Si doped GaAs ohmic contact layer, which are respectively epitaxial layers, are respectively sequentially deposited over a semi-insulating GaAs substrate. An outer recess section is formed by removing the Si doped GaAs ohmic contact layer by etching, and an inner recess section is formed by removing the surface of the undoped AlGaAs Schottky contact layer exposed to within the outer recess section by etching, respectively. Further, ohmic electrodes are provided on the Si doped GaAs ohmic contact layer, and a gate electrode is provided on the undoped AlGaAs Schottky contact layer lying in the inner recess section, respectively.
Since a field intensity lying within the channel layer at the application of a voltage is reduced in the FET having such a double recess structure, an improvement in the breakdown voltage of a transistor can be expected. As other examples of the compound semiconductor FET having the double recess structure, there have been known examples described in patent documents (Japanese Unexamined Patent Publication No. Hei 9(1997)-45894, Japanese Unexamined Patent Publication No. Hei 11(1999)-214676, and Japanese Unexamined Patent Publication No. 2004-193273).
However, the compound semiconductor FET having the double recess structure is unstable in transistor characteristics because the transistor characteristics thereof greatly depend on the surface state at the outer recess section. This results from the following reasons:
In the compound semiconductor FET having the double recess structure, the surface of the outer recess section is of a compound semiconductor. In general, a high-density surface level ranging from about 1011 cm−2 to 1013 cm−2 exists in the surface of the compound semiconductor. Its surface state density greatly varies according to the adhesion of dust, the condition of the process for the surface, and the like. In the compound semiconductor FET having the double recess structure, a depletion layer expands below the outer recess section, and the width of the depletion layer also changes when the surface state density of the outer recess section changes. Since a channel layer placed below the depletion layer is narrowed when the width of the depletion layer is enlarged, a drain current decreases. Since the channel layer expands when the width of the depletion layer is scaled down in reverse, a drain current increases.